1. Field of the Invention
The present invention relates to an integrated circuit test system. More specifically, the invention relates to the test system having a single memory used for both a parallel testing mode and a scan testing mode.
2. Description of the Related Art
The prior art in U.S. Pat. No. 5,606,568, assigned to the present assignee, shows a testing method and structure for performing level sensitive scan design (LSSD) testing of electronic circuits using parallel test vector memory. FIG. 1 shows a prior art system 100 for testing an electronic device under test (DUT) 101. Test system 100 includes test vector pointer memory 102 which stores a plurality of predefined test instructions defining the electronic tests to be performed on DUT 101. Pattern processor 105 receives, in response to a fetch signal applied to test vector pointer memory 102 via fetch line 103 an instruction via instruction bus 104 from test vector pointer memory 102. In response to the instruction, pattern processor 105 provides one or a sequence of addresses via address bus 106 to test vector data memory 107 in order to access one or more test vectors previously stored in test vector data memory 107. These one or more test vectors are sequentially sent via data bus 108 to timing generators 109 which serve to convert the test vector data into appropriately timed signals having appropriate voltage and current levels which are in turn applied via bus 110 to appropriate leads of DUT 101. Such a prior art test system as shown in FIG. 1 is well known in the art and is described, for example, in R. Powell. "IBM's VLSI Logic Test System." IEEE Test Conference Proceedings, pp.388-392 (1981). As shown in FIG. 2, during normal operation, parallel test vectors are addressed from test vector data memory 107 by pattern processor 105 and in turn applied via leads 108-1 through 108-N of bus 108 to individual timing generators and associated electronics 109-1 through 109-N which in turn apply desired signal levels to input leads 201-1 through 201-N of DUT 101.
Several types of instructions can be stored in test vector pointer memory 102 for controlling pattern processor 105. One such instruction is the test-vector-strip (TVS) instruction, which has the following format: EQU TVS&lt;count&gt;&lt;address&gt;
where TVS is the instruction type, &lt;count&gt; is the number of sequential vectors within test vector data memory 107 to be sequentially addressed by pattern processor 105, and &lt;address&gt; is the address within test vector data memory 107 containing the first one of the sequential vectors. For example, A TVS instruction TVS 15 1102 causes pattern processor 105 to sequentially address 15 vectors stored within test vector data memory 107, beginning at address 1102 and thus ending at address 1116. With the advent of large scale integrated circuits problems of device testing have been compounded. For example, as the number of components and input leads in an integrated circuit increases there are greater numbers of combinations and permutations of input data sequences and output data sequences. It becomes increasingly difficult to test all such combinations and permutations as well as consuming greater time in programming the test sequence, storing the number of test vectors, and taking increased time to test each integrated circuit. These problems add to the cost of integrated circuit testing.
In order to reduce some of these problems with testing LSI devices, integrated circuits have been designed using the level sensitive scan design (LSSD) technique as described by E. Eichelberger and T. Williams. "A Logic Design Structure for LSI Testability", Journal of Design Automation and Fault Tolerant Computing. Vol.2 No.2 pp. 165-178 (May 1978). Using this LSSD technique, DUT 101 of FIG. 2 is designed to include a plurality of gates or latches 203-1 through 203-N each associated with input lead 201-1 through 201-N of DUT 101. Input signals on input leads 201-1 through 201-N are applied to latches 203-1 through 203-N via input buffers 202-1, 202-N. The output leads of latches 203-1 through 203-N are connected to internal circuitry (not shown) of DUT 101, thereby allowing the parallel input signals applied to parallel input leads 201-1 through 201-N of DUT 101 to cause DUT 101 to operate in a normal fashion. However, in addition DUT 101 includes serial LSSD input lead 204 and serial LSSD output lead 205 having latches 203-1 through 203-N connected serially therebetween. While FIG. 2 shows only a single chain of latches 203-1 through 203-N and single pair of LSSD input and output leads such as leads 204,205, it is to be understood that DUT 101 can have any desired number of LSSD channels including latches for temporarily storing logic level at any desired locations within DUT 101. Each such LSSD channel includes a plurality of latches such as latches 203-1 through 203-N, and LSSD input and output leads 204,205, as well as an associated input buffer and output buffer. By utilizing such LSSD channels, normal parallel data input operation of DUT 101 can be suspended while the contents of such latches are preset by rippling in serial input signals from LSSD input lead 204 and sequentially reading on LSSD output lead 205 the contents of each LSSD register 203-1 through 203-N. This allows the test system the ability to preset data values at desired locations internal to DUT 101 without the need for causing such data values to be preset in response to parallel input test vectors applied to input leads 201-1, 201-N. Normal parallel input signal operation of DUT 101 is performed as previously described utilizing test vector data memory 107 which applies parallel test vectors to parallel input leads 201-1 through 201-N. However, as shown in FIG. 3 when it is desired to test DUT 101 using LSSD input and output leads 302, 304, separate serial LSSD input memory 305-1 and LSSD output memory 305-2 is used. During LSSD testing the contents of LSSD input memory 305-1, which is configured to be one bit wide per LSSD channel and typically on the order of 100 Mbits deep, are sequentially applied to LSSD input lead 302. Simultaneously, the contents of the latches in the LSSD channel are sequentially outputted on LSSD output lead 304 and compared to expected LSSD output memory 305-2 which is one bit wide per LSSD channel and typically the same depth as is LSSD input memory 305-1.
Unfortunately, this prior art technique for performing LSSD testing requires the use of additional memories 305-1, 305-2, thereby adding to cost and complexity of the test system.
U.S. Pat. No. 5,606,568 further describes a single memory used for both parallel input test vector testing and serial LSSD test vector testing of an LSSD device. The patent shows a memory having both serial scan chains and parallel vectors distributed throughout the memory with large blocks of memory that are unfilled with data. This memory was part of a system used to decrease the time needed to reload the memory. This memory has the disadvantage that it does not use memory space efficiently. To decrease reload time it sacrifices space efficiency.
What is needed is a test system with a single memory which will allow a tester to have both a parallel test mode and a scan test mode that is efficient in its use of space and provides both parallel and scan vectors to the test system fast enough to conduct testing on integrated circuits economically and efficiently.